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Additional resources for ACM-SIGDA Physical Design Workshop #4 1993: Layout Synthesis for the New Generation of VLSI ASIC Technologies (Workshop Proceedings)

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An optimal algorithm for floorplan optimization. In Proceedings of 27th ACM/IEEE Design Automation Conference, pages 180-186, 1990. C. F. Wong. Efficient shape curve construction in floorplan design. 5 _ - - 966 j17242 281 J 1431 2 125 1585 6782 2 15 265 265 3 11 the European Conference on Design Automation, pages 356-360, 1991. High Performance Multichip Interconnection Design D. Zhou and F. Tsui Department of Electrical Engineering The University of North Carolina at Charlotte Charlotte, NC 28223 D.

Certainly, once a module placement has been fixed, good timing-driven interconnection algorithms are key to enhancing the performance of the layout solution. For a given signal net, the typical objective has been to minimize the maximum signal delay to any sink. , Dunlop et al. (9] determine net priorities based on static timing analysis, and process higher priority nets earlier using fewer feedthroughs; Jackson, Kuh and MarekSadowska [123 outline a hierarchical approach to timing-driven routing; and Prastjutrakul and Kubitz (161 use A* heuristic search and the Elmore delay formula [10] in their tree construction.

On High-Speed VLSI Interconnects: Analysis and Design. , 1992. C. Edwards. Foundationsfor Microstrip'Circuit Design. Wiley, 1984. S. T. M. Kang. Modeling and simulation of interconnection delays and crosstalks in high-speed integrated circuits. IEEE Trans. on Circuits and Systems, 37(1):1-10, 1990. [GZ93] D. Gao and D. Zhou. Propagation Delay in RLC Interconnection Trees. to appear in ISCAS-93, 1993. [Nag75] L. W. Nagel. Spice2, A computer program to simulate semiconductor circuits. Tech. Rep. ERL-M520, University of Calif.

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ACM-SIGDA Physical Design Workshop #4 1993: Layout Synthesis for the New Generation of VLSI ASIC Technologies (Workshop Proceedings) by ACM-SIGDA

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